Senior FPGA Engineer

Olee.Space 

📍 Pune City, India 🇮🇳

full-time
senior
on-site
Posted —

Key Skills

FPGAVHDLVerilogDSPSerDes

Industry

AerospaceTelecommunications

Job Description

We're Hiring: Senior FPGA Engineer — Free Space Optical Communications (FSOC)

Location: Pune, India (In-office)

Type: Full-time


We're building high-throughput Free Space Optical Communication systems laser-based links for [satellite / inter-satellite / ground-to-air / terrestrial backhaul] applications. We need an FPGA engineer who has actually done this before: someone who has taken an FSOC modem or link from concept through silicon, lab, and real-world deployment.

This is not a role for someone learning FSOC on the job. We're looking for hands-on, build-and-ship experience.

What you'll do

  • Architect and implement FPGA-based modems and signal processing chains for optical links (modulation/demodulation, FEC, acquisition, tracking, timing recovery)
  • Design high-speed digital logic interfacing with ADCs/DACs, optical front-ends, and pointing/acquisition/tracking (PAT) subsystems
  • Optimize for throughput, latency, and link budget under real atmospheric/pointing conditions
  • Bring up hardware in the lab and support field/range testing through to a working link
  • Work shoulder-to-shoulder with optics, photonics, RF, and systems engineers

What we're looking for (must-haves)

  • Proven, hands-on experience building FPGA systems for FSOC or closely related optical/coherent comms — shipped or deployed, not just simulated
  • Strong RTL design in VHDL and/or Verilog/SystemVerilog
  • Deep DSP-for-comms knowledge: FEC (LDPC/Reed-Solomon/Turbo), synchronization, equalization, timing/carrier recovery
  • Experience with high-speed interfaces (SerDes, JESD204B/C, high-speed transceivers) and multi-Gbps data paths
  • Comfortable with the full flow: architecture, RTL, timing closure, lab bring-up, debug (ILA/ChipScope, scopes, logic analyzers)
  • Track record of getting a real optical link working end-to-end

Nice to have

  • Experience with Xilinx/AMD (Versal, UltraScale+) or Intel/Altera FPGAs
  • Familiarity with PAT, beam steering, or adaptive optics
  • Background in satellite, aerospace, or defense comms
  • Knowledge of optical link budgets and atmospheric turbulence mitigation

A note on who we want

  • We deeply respect academic research, but this role specifically needs someone who has built and debugged real FSOC hardware that had to work outside a simulation or a paper. If you've made photons carry data across a real link and fought the bugs that come with it, we want to talk to you.