Senior Design Engineer - ASIC IP

Company:IT Services Organization

Key Skills: Lint, RTL Design, RTL, Spyglass, VHDL, CDC

Roles and Responsibilities:

• Develop ASIC IP blocks and subsystems for 5G and 6G communication technology
• Take full ownership of design at the block or subsystem level
• Generate comprehensive documentation throughout the design lifecycle
• Perform digital design and conduct all RTL sign-off checks
• Continuously enhance and optimize design methodologies and processes
• Collaborate with IP Architects to break down requirements and create detailed IP architecture and design specifications
• Work closely with verification engineers to review and refine verification plans
• Build competence in the technical domain
• Engage in cross-team collaboration to ensure successful project delivery

Skills Required:

• Strong expertise in RTL design and RTL coding practices
• Experience with linting tools and RTL sign-off checks
• Familiarity with VHDL, CDC analysis, and Spyglass tools (nice-to-have)
• Ability to take full ownership of block/subsystem designs
• Knowledge of ASIC IP development for 5G/6G technologies
• Experience in generating comprehensive design documentation
• Strong collaboration with IP architects and verification engineers
• Problem-solving skills to optimize design methodologies and processes
• Ability to engage effectively in cross-team collaboration

Education: Bachelor's degree in Electrical or Computer Engineering