Senior Analog & Mixed Signal IC Design Engineer

Teradar is pioneering a new era in perception with the world’s first automotive terahertz vision sensor, delivering ultra-high resolution imaging in any weather condition. Founded in Boston, Teradar’s solid-state, chip-scale technology unlocks safer, smarter vehicles and opens the door to transformative applications in mobility, defense, and beyond.

You will lead the development of critical low-power AMS circuits, defining the clocking, PLL, and data converter architectures that power our novel terahertz sensor.

This is a high-impact role where you will collaborate across RF, systems, and digital teams to bring next-generation sensor SoCs from initial concept to high-volume silicon.

Responsibilities

• Architectural Leadership: Lead the definition and design of low-jitter clocking architectures, high-speed PLLs, and data converter signal chains, ensuring seamless integration with RF front-ends and digital back-ends.
• Circuit Design: Design and implement high-performance, low-power blocks including frequency-synthesized PLLs, VCOs, telemetric/diagnostic ADCs, programmable gain amplifiers (PGAs), bandgap references, and bias circuits.
• System Integration: Derive block-level specifications from complex system requirements and spearhead architecture-level trade-off discussions regarding noise, jitter, and power distribution.
• Full Lifecycle Ownership: Own the schematic design, pre-/post-layout simulation, and rigorous verification of clocking and data converter subsystems using industry-standard EDA tools.
• Physical Design Oversight: Work closely with layout engineers to ensure robust, noise-immune, and area-efficient physical implementations of jitter-sensitive circuits.
• Silicon Bring-up: Lead silicon validation, debugging, and characterization of clocking networks and ADCs in the lab to ensure hardware meets performance targets.

Key Qualifications

• System Expertise: Proven experience in AMS design specifically for low-jitter clock generation (PLLs) and data conversion (ADCs) architectures. Deep understanding of frequency synthesis and signal conditioning.
• Experience: 10+ years of hands-on experience in analog and mixed-signal IC design, specifically in advanced nodes (e.g., TSMC 28nm or below).
• Block Expertise: Deep technical expertise in PLLs (integer/fractional-N, LC/Ring VCOs), high-precision or telemetry ADCs, PGAs, bandgap design, and biasing circuits.
• Tools: High proficiency with Cadence Virtuoso, Spectre, SpectreRF, and AMS simulation environments.
• Low-Power Mastery: Solid background in low-power design methodologies and the jitter/power trade-offs inherent in sensor clocking applications.
• Education: PhD in Electrical Engineering (or equivalent) preferred; MS required with significant industry track record.

Location

• San Jose, CA (hybrid)