Senior Analog Design Engineer

JPS Tech Solutions 

📍 Santa Clara, United States 🇺🇸

contract
senior
remote
Expired
Posted —
This job posting has expired View All Analog Design Engineer Jobs

Key Skills

CMOSADCsDACsPythonCadence

Industry

SemiconductorConsumer Electronics

Job Description

Job Category: Analog Design Engineer

Job Type: Remote

Job Location: California Santa Clara

Compensation: Depends on Experience

W2: W2-Contract Only; Kindly note that applications on a C2C basis will not be considered for this role.

Eligible Visa: GC GC-EAD H1B H4 EAD L2S U.S. Citizen (USC)

Job Description

Visa Requirement:

This position is open only to candidates authorized to work in the United States under the following categories: U.S. Citizen, Green Card Holder, GC-EAD, H-1B (Transfer), H-4 EAD, L-2s, L-2 EAD, or J-2 EAD. Candidates requiring other visa sponsorship are not eligible for this role.

Job Description:

We are seeking a Senior Analog Design Engineer with strong expertise in analog and mixed-signal CMOS design to develop advanced integrated circuits for semiconductor fabrication equipment. This is a hands-on role for an experienced engineer who enjoys solving complex analog challenges and owning designs from concept through silicon bring-up and characterization, while collaborating closely with cross-functional teams to deliver high-quality, manufacturable silicon.

Key Responsibilities:

Design and develop analog and mixed-signal CMOS circuits for production silicon

Create, simulate, and optimize ADCs, DACs, bandgap references, and voltage/current reference circuits

Design current drivers, linear regulators, and other critical analog blocks

Perform circuit simulation and verification using Cadence Spectre and ADE

Translate process technology limitations into robust, manufacturable circuit designs

Collaborate with system, layout, and verification teams to ensure successful design execution

Review, guide, and approve custom analog layouts at block and chip levels

Develop Python-based test and characterization code for silicon validation

Support silicon bring-up, bench testing, performance debugging, and failure analysis

Analyze silicon results and troubleshoot issues across multiple silicon revisions

Ensure designs meet reliability, ESD, and latch-up requirements

Plan and manage design tasks to meet schedule, quality, and performance goals.

Required Qualifications:

M.S. in Electrical Engineering or equivalent practical industry experience

10+ years of hands-on experience in analog and mixed-signal CMOS IC design

Strong experience designing ADCs, DACs, current drivers, and linear regulators

Solid understanding of IC device physics, SPICE modeling, ESD, and latch-up protection

Proficiency with Cadence Virtuoso (schematic and layout) and Spectre/ADE

Experience designing and verifying analog circuits in advanced CMOS process nodes

Working knowledge of digital RTL design (SystemVerilog)

Proficiency in Python for silicon verification, testing, and characterization

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