Senior ASIC Design Engineer

Company Description

InnoGrit is a fabless IC design startup leading advancements in storage technology to address the growing demands of next-generation applications. The company has introduced a range of high-performance SSD controllers and data acceleration engines tailored for diverse industries, including Client, Enterprise/Data Center, and OEM/ODM markets. InnoGrit specializes in intelligent, low-power, and end-to-end SSD controller solutions that help businesses enhance their storage efficiency while reducing costs. By enabling data computation within storage systems, InnoGrit’s innovative solutions help customers stay ahead of current and future application needs.

Role Description

This is a full-time, on-site role based in Santa Clara, CA, for a Senior ASIC Design Engineer. The Senior ASIC Design Engineer will engage in RTL design, logic design, and physical design tasks, as well as participate in formal verification. The engineer will collaborate with cross-functional teams to define, design, and deliver cutting-edge ASIC solutions for advanced SSD controllers and related technologies. Responsibilities include developing efficient design solutions, verifying functionality, and ensuring compliance with specifications.

Responsibilities

1. Contribute to the microarchitecture design of next-generation SSD controllers and storage subsystems, with a focus on optimizing architectures for AI applications.

2. Develop and write detailed design specifications, microarchitecture documents, and implementation guidelines.

3. Design and implement key functional blocks using Verilog/SystemVerilog RTL.

4. Work closely with the verification team to define test plans, coverage analysis, and support full-chip simulation, debug, and validation.

5. Collaborate with the physical design team to ensure timely and high-quality RTL-to-GDS implementation.

6. Support post-silicon bring-up, debugging, and performance validation in the lab.

7. Work closely with firmware and system teams to ensure feature alignment and product-level performance targets are met.

8. Perform design analysis and optimization to improve performance, power efficiency, and area (PPA).

Qualifications

• Proficiency in RTL Design and RTL Coding
• Expertise in Logic Design and Physical Design
• Experience with Formal Verification methodologies and tools
• Strong analytical, problem-solving, and debugging skills
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 3+ years of experience in ASIC design or a related field
• Familiarity with SSD controllers, data storage technologies, or similar systems is a plus
• Ability to work collaboratively in a team environment and communicate technical ideas effectively

Preferred Qualifications

1. Experience in SSD controller or storage system design.

2. Familiarity with AI/ML workload acceleration, memory/storage hierarchy, or data path optimization.

3. Hands-on experience with synthesis (Design Compiler), STA, CDC, lint, and formal verification flows.

4. Knowledge of UVM-based verification methodologies.