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RTL Manager

Quest Global ↗

📍 Bengaluru, India 🇮🇳

full-time

senior

Expired

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Key Skills

SoCSystemVerilogUPFLintCDC

Industry

SemiconductorConsumer Electronics

Job Description

Job Requirements

Role Overview

We are seeking a highly motivated and skilled SoC RTL Integration & Design Sign-off Engineer to join our cutting-edge semiconductor design team in Bangalore. The ideal candidate will be responsible for the top-level integration of complex System-on-Chip (SoC) designs and ensuring the design quality through various critical sign-off checks (Lint, CDC, RDC, and Low Power VCLP flows).

🔑 Key Responsibilities

SoC Top-Level Integration: Own the SoC Top RTL integration using System Verilog for complex multi-core, multi-voltage, and multi-clock domain architectures.
Low Power Design & Verification: Implement and verify the Low Power intent using the Unified Power Format (UPF) and ensure the design adheres to the defined power strategy through comprehensive RTL VCLP (Voltage/Current Leakage Power) checks and low-power verification flows.
Design Quality Sign-off: Execute and drive closure for critical pre-synthesis quality checks across the SoC.

Linting: Perform static design checks to ensure adherence to RTL coding guidelines and best practices.
CDC/RDC Checks: Implement, analyze, and resolve all violations related to Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) to ensure robust asynchronous interfaces.

Methodology & Flow Development: Collaborate with the CAD/EDA team to enhance and maintain the SoC integration, low-power, and sign-off methodologies and tool flows.
Cross-Functional Collaboration: Work closely with Micro-architecture, IP Design, Verification, Physical Design, and DFT teams to ensure a clean, on-time handoff for tape-out.
Documentation: Develop and maintain technical specifications, sign-off reports, and methodology documents.