The Role:
We are looking for an RTL / FPGA Engineer to design and implement high-performance digital signal-processing and communication systems on modern FPGA and adaptive SoC platforms.
You will work on digital beamforming, channelization, synchronization, modulation and demodulation, forward-error correction, and high-speed data movement. This is a hands-on role covering architecture, RTL development, simulation, timing closure, hardware integration, and laboratory validation.
Responsibilities
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Design and implement synthesizable RTL in SystemVerilog or VHDL for FPGA-based communication systems.
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Develop digital and hybrid beamforming pipelines for multi-element phased arrays.
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Implement complex weighting and beam summation, digital up- and down-conversion, FFT/IFFT and polyphase filter banks, channelization and sample-rate conversion, synchronization, modulation and demodulation, FEC, and calibration logic.
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Architect high-throughput, low-latency datapaths for multi-channel I/Q processing.
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Integrate RTL modules with RF data converters, processors, memories, Ethernet interfaces, and high-speed serial links.
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Develop AXI4, AXI4-Stream, and memory-mapped control interfaces.
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Create testbenches, verification environments, reference models, and automated regression tests.
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Perform synthesis, place-and-route, resource optimization, clock-domain-crossing analysis, and timing closure.
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Validate designs using simulation, FPGA hardware, RF test equipment, logic analyzers, and captured I/Q data.
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Collaborate with RF, antenna, DSP, software, systems, and hardware engineers.
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Document module interfaces, architectural decisions, test results, and performance measurements.
Required Qualifications
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Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Communications Engineering, or a related field.
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Strong experience developing production-quality RTL using SystemVerilog, Verilog, or VHDL.
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Experience with FPGA development using AMD/Xilinx Vivado or a comparable toolchain.
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Good understanding of fixed-point signal processing, pipelining, latency, resource utilization, and numerical precision.
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Familiarity with digital communication concepts such as OFDM, QAM, synchronization, filtering, channel estimation, and error correction.
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Experience implementing DSP algorithms on FPGA hardware.
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Understanding of clock-domain crossing, reset architecture, timing constraints, and timing closure.
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Experience with hardware debugging tools such as ILA, VIO, oscilloscopes, spectrum analyzers, or vector signal analyzers.
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Ability to translate MATLAB, Python, C/C++, or algorithm-level models into efficient RTL architectures.
Preferred Qualifications
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Experience implementing digital beamforming or phased-array signal processing.
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Knowledge of hybrid beamforming, antenna calibration, beam steering, sidelobe control, and multi-beam architectures.
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Experience with satellite, wireless, radar, 5G/NR, DVB-S2X, or other high-throughput communication systems.
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Experience with AMD Versal, RFSoC, Zynq UltraScale+, AI Engines, or similar heterogeneous platforms.
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Familiarity with JESD204B/C, Aurora, PCIe, Ethernet, DDR, and high-speed transceivers.
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Experience with FEC algorithms such as LDPC, Polar, BCH, or Reed-Solomon codes.
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Familiarity with cocotb, UVM, MATLAB, Python, or formal verification.
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Experience taking an FPGA design from initial architecture through hardware demonstration or deployment.
What We Value
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Strong ownership and the ability to solve open-ended engineering problems.
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A practical, hardware-oriented approach to signal processing.
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Attention to verification, interfaces, numerical behavior, and system-level performance.
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Comfort working in a fast-moving startup environment and contributing across traditional engineering boundaries.
Why Join Us
You will have the opportunity to work on the bleeding edge of communication technology from the ground up, work directly with phased-array and RF hardware, and influence the architecture of satellite communication and onboard-compute systems.