Lead ASIC DFT Engineer

Lead ASIC DFT (Design-for-Test) Engineer - Job Description

Job Details

 Experience: 10+ Years

 Job Type: Contract (C2C)

 Work Location: Remote

 Pay : $40.00/hour

About the Role

 We are seeking an experienced Lead ASIC DFT Engineer with 10+ years of hands-on experience in ASIC test architecture, scan insertion, ATPG, and silicon bring-up.

Key Responsibilities

 Define and implement DFT architecture for complex ASIC and SoC designs.

 Lead scan insertion, compression, JTAG, MBIST, and LBIST implementation.

 Develop and validate ATPG patterns.

 Support silicon bring-up and production testing.

 Mentor junior engineers and provide technical leadership.

Required Qualifications

 Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering.

 10+ years of ASIC/SoC DFT experience.

 Expertise in Scan, ATPG, MBIST, LBIST, JTAG, DFT verification, and fault analysis.

 Experience with Synopsys TestMAX/Tetramax, Cadence Modus, and Siemens Tessent.

 Strong understanding of ASIC design and verification flows.

Key Skills

 ASIC DFT

 ATPG

 Scan Insertion

 MBIST/LBIST

 JTAG

 Tessent

 Cadence Modus

 Synopsys TestMAX

 Silicon Bring-up