Digital ASIC Design Engineer

3Brain is a Swiss deep tech company working on cell-electronic interfaces that link biological networks to computers via custom-made semiconductor microchips. Our mission is to empower life scientists to probe intelligent networks, accelerate biomedical discoveries for the benefit of patients, and create a future more exciting than the present. Our interdisciplinary team of scientists and engineers are constantly pushing the boundaries of engineering for life’s complexities. We are ambitious, fast-growing and love to explore. The company’s cutting-edge products are used in laboratories and pharma companies worldwide. 3Brain is headquartered in Switzerland nearby Zurich, has a Discovery Unit and production site in Genova, Italy, and an operational unit in the US.

3Brain is looking for a Digital ASIC Design Engineer to reinforce our R&D team and grow within the company. The candidate will be part of a group of ASIC design engineers and help optimizing existing sensors and designing the future CMOS-sensor products of 3Brain. Main responsibilities:

• Optimization and improvement of existing digital sensor systems.


• Design, system verification, and implementation of digital building blocks for new CMOS-based biological sensor systems.


• Documentation of design methods, specifications, functional requirements and design choices.


• Generation of detailed test specifications and reports.


• Keeping up to date with relevant literature and the latest circuit designs.

Required Qualifications

• 3 or more years of professional experience in digital ASIC workflow.


• BSc/MSc/PhD in Microelectronics.


• Core Expertise: Digital Signal Processing Fundamentals, Digital Verification, Static Timing Analysis (STA), Synthesis, Place & Route, Clock Tree Synthesis (CTS), Power Integrity, Signoff.


• Proficiency in Verilog, SystemVerilog, TCL, Python


• Fluency in English.


• Great team spirit, outstanding personality and willingness to learn


• Initiative, independence and ability to communicate and work effectively with other team members in a multicultural and international environment.


• Applicant must already have a work permit for the Schengen area.

Additional Qualifications

• Knowledge of low-power design techniques and Design for Test (DFT)


• Experience with Universal Verification Methodology (UVM)


• Experience with simulation tools from major vendors like Synopsys (VCS), Cadence, or Mentor Graphics.


• Proficiency in VHDL

• A dynamic and stimulating work environment driven by a desire to build transformational technologies to help others.


• A young, fast-growing company with plenty of opportunities for personal growth and development.


• Great challenges and adventures in both technical and economical fields.


• Working place: Pfäffikon SZ, Switzerland . It is a beautiful lakeside village just outside of Zurich, the country’s main cultural, financial and business center.