Design Verification Engineer

*Key Responsibilities:* 📎
Languages/Methodology: Verilog, System Verilog, HDL, UVM

Protocols:
AMBA protocols: APB, AHB, AXI
High-speed interfaces: PCIe, Ethernet
Memory interfaces: DDR, LPDDR
Other protocols: USB, I2C, UART, Wi-Fi

Skills:
• UVM based Test Bench development, Test case writing, Code Coverage, Functional Coverage, Assertion
• RTL/TB/Test case Debugging, Develop reusable Monitor
• Scoreboard, Driver, Sequences
• Regression Pass/ Fail debugging

Mandatory Requirements:
1.Must have worked in client place.
2.Exposure to at least 2–3 real-time projects

Experience: 2-5 years of relevant industry experience