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MIPS

CPU RTL Design Engineer

๐Ÿ“ŒAustin, United States ๐Ÿ‡บ๐Ÿ‡ธ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ mid-level

hybrid

Drive the Next Wave of Computing Innovation at MIPS

At MIPS, weโ€™re shaping the future of compute architecture with advanced IP that powers a wide range of applications. We take a disciplined, methodical approach to designing scalable, energy-efficient solutions that meet demanding power, performance, and area goals.

Our team spans from architecture, performance modeling, design, verification, implementation to software and software optimization for our customers. The team thrives on collaboration, technical depth, and a culture of mutual respect. We value diverse perspectives and practical experience, and we know that excellence is built through thoughtful teamwork and a commitment to the highest engineering standards.

Weโ€™re seeking a CPU RTL design engineer with prior experience in creating structural RTL for one of the following: CPU, GPU, DSP, Interconnects, memory controllers or compute accelerators.

As part of our team, youโ€™ll have the opportunity to take ownership of CPU functional blocks and implement RTL, and work with verification and physical design engineers to ensure adherence to functional and physical project requirements.

Our flexible hybrid work modelโ€”three days in the office, two remoteโ€”supports both in-person collaboration/mentoring and focused development time.

Join us and put your skills, insight, and passion to work to redefine whatโ€™s possible

Description

As a CPU design engineer you own or participate in the following:

  • RTL design of one or many functional blocks based on the microarchitectural specification. Ownership includes the RTL design, implementation and convergence of the block to project requirements (performance, timing, power, area, schedule)
  • Support of the verification team for test bench development, test plan development and test content development, including performance verification
  • Work with physical design teams, and design for testability teams to implement and converge physical design and testability

Minimum Qualifications

  • Minimum BS and 2+ years of relevant industry experience
  • Experience in structural data path and/or control logic design
  • Experience with Verilog, System Verilog, or VHDL
  • Experience with commercial simulators and debugging tools
  • Good verbal and written communication skills to interface with performance modeling, verification and physical design team

Preferred Qualifications

  • Experience with timing convergence
  • Experience with low power design techniques
  • Experience using scripting languages and regular expressions
  • Programming experience with assembly, C, or C++
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  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ mid-level

  • Working model

    hybrid

  • Skills
  • Industry
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