Analog Layout Design Engineer
Source-Right ↗
📍 Bengaluru, India 🇮🇳
full-time
mid-level
Expired
Posted —
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Key Skills
CadenceSerDesDDRPCIeESD
Industry
SemiconductorConsumer Electronics
Job Description
Position: Analog Layout Design Engineer (SI510FF RM 3682)
Required Qualifications
Required Qualifications
- 5 to 10 years of experience in analog layout design.
- Proven experience in advanced nodes (7nm, 5nm, or below) is a must.
- Proficiency in layout tools such as Cadence Virtuoso, ICV, Calibre, Assura, etc.
-
Strong understanding of analog layout constraints and techniques for high-performance and low-noise designs.
- Experience in high-speed IO layout (e.g., SerDes, DDR, PCIe).
- Exposure to MBCFET and FinFET layout challenges and solutions.
- Understanding of ESD and latch-up prevention techniques.
Featured Opportunities
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Key Skills
CadenceSerDesDDRPCIeESD
Industry
SemiconductorConsumer Electronics
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