该职位来源于猎聘 Responsibilities:
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Work with ASIC designer to define validation methodology and develop test plans for DDR controllers including DDR PHY and related logics.
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Develop and maintain DDR (DDR5/4, LPDDR5/4) interface training firmware. Develop system DDR validation tests based on SSD SoC and modules.
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SoC DDR interface bring up, characterization & validation test plan execution, data collection and result analysis.
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Work with cross teams to analyze DDR related issues reported by customers, rootcause the issues and improve validation test coverage.
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Work with validation team to complete the DDR AVL testing including Digital SI test and Electrical Compliance Test.
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Lab automation test tool development
Required Experience
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Master or Bachelor’s degree in CS/CE/EE or related engineering discipline.
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Good understanding of protocol and training theory of DDR5/4 and LPDDR5/4.
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Knowledge of embedded systems, ex: ARM/Risc-V CPU,
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Strong programming experience of C, Python and scripts.
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Knowledge of SSD technology, flash technology or storage interface protocols (SATA, SAS, PCIe/NVMe) is a plus
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Familiar with Windows, Linux and Git.
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Experience with lab tools such as oscilloscopes and logic/bus analyzers is a plus
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Oral and written communication skills in both English and Chinese.