Responsibilities
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Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs
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Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility
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Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs
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Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout
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Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications
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Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product
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Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth
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Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability
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Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency
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Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery
Requirements
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MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
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Experience with Verilog and system Verilog
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Experience with VCS, Verdi or other industry standard tools
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Experience with pre-layout simulation and post-layout simulation
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Understanding of the design flow. Ability to work with the backend team
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Familiarity with AMBA APB AXI Protocol
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Familiarity with RISC/Arm or other core architectures
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Ability to create innovative architecture and solutions to customer requirements
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Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.
Experience in one or more of the following areas considered a strong plus:
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FPGA/ASIC design of image processing systems
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Working knowledge of SoC architecture such as CPU, GPU or accelerators
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Familiarity with: UVM, place-and-route, STA, EM/IR/Power
Salary Range:
$110,000 - $300,000 / year