ASIC RTL Design Engineer

Company Description

Sauvira Solutions Private Limited is a fast-growing semiconductor services startup driving India’s semiconductor transformation. The company delivers end-to-end solutions across semiconductor design, verification, and testing, helping clients accelerate time-to-market and improve product performance. Its expertise spans SoC development, RTL design and integration, FPGA implementation, formal verification, timing and power analysis, and advanced testability solutions. Backed by a team of experienced engineers and domain specialists, Sauvira Solutions focuses on innovation, quality, and close client collaboration. The organization is committed to using cutting-edge methodologies to provide efficient, reliable, and cost-effective semiconductor solutions.

Role Description

This is a full-time, on-site ASIC RTL Engineer role. The ASIC RTL Engineer will be responsible for designing and implementing RTL for complex digital blocks and subsystems, ensuring functional correctness, performance, and power efficiency. Daily responsibilities include writing synthesizable RTL, integrating IPs and interfaces, participating in micro-architecture definition, and collaborating with verification teams to close functional coverage and debug simulation failures. The role also involves working with physical design, DFT, and validation teams to support synthesis, timing closure, and testability requirements, as well as contributing to design reviews and documentation. The engineer will work closely with cross-functional stakeholders to ensure high-quality deliverables and timely project execution.

Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or a related discipline
• Must have 4 to 6 years of experience in ASIC RTL Design .
• Strong digital design fundamentals, including experience with RTL design, micro-architecture, and System-on-Chip (SoC) or block-level design.
• Proficiency with hardware description languages such as Verilog and/or SystemVerilog, and experience writing clean, synthesizable RTL.
• Familiarity with ASIC design flows , including synthesis, static timing analysis, linting , and formal checks.
• Experience collaborating with verification teams, understanding testbenches , and supporting debug for simulation and regression failures.
• Understanding of low-power design concepts, clock-domain crossing , and design-for-test (DFT) considerations is beneficial.
• Comfort using industry-standard EDA tools (for design, synthesis, and analysis) and version control systems.