ASIC Design Verification Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 8 years of design verification experience.
• Experience verifying digital logic at RTL using SystemVerilog and UVM for ASICs.
• Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, caches, Coherency, hierarchical memory subsystems, DDR/LPDDR).

Preferred qualifications:

• Master's degree in Electrical Engineering or Computer Science with 10 years of relevant work experience.
• Experience creating and using verification components and environments in a standard verification methodology such as UVM.
• Experience with performance verification of ASICs and ASIC components and experience with ASIC standard interfaces and memory system architecture, LPDDR.
• Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification using Industry leading formal tools.
• Experience with GLS, low-power DV, and support of SOC DV.
• Experience in formal verification.

About the job:

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities:

• Plan the verification of complex Memory Subsystem IPs at IP and Subsystem level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
• Work closely with design, architecture, software, silicon validation, back-end implementation stakeholders to make technical decisions and to come up with detailed test plans, dependencies and deliverables.
• Create and enhance constrained-random verification environments using System Verilog and UVM, or formally verify designs with SVA and industry leading formal tools.
• Identify and write all types of coverage measures for stimulus and corner-cases ;  close coverage measures to identify verification holes and to show progress towards tape-out.
• Primary point of contact on functional verification to cross-functional teams and drive verification methodologies and improvements. Debug tests with design engineers to deliver functionally correct design blocks.