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ASIC Physical Design Methodology Engineer

NVIDIA ↗

📍 Shanghai, China 🇨🇳

full-time

mid-level

Expired

Posted —

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Key Skills

ASICCMOSFinFETEDATCL

Industry

SemiconductorAutomotive

Job Description

Responsibilities

ASIC-PD methodology team are responsible for the development of timing analysis and timing closure methodologies and flow automation for super large and high speed semi-custom chips using deep submicron processes. This includes:

Research and implement state-of-the-art timing signoff methodology on deep sub-micron process
Build automatic flow with commercial timing signoff tools to achieve high quality timing closure
Develop internal tools and methodology to automate timing constraint/SDC generation
support the physical design implementation team for speed of light project execution

What You'll Be Doing

Develop and validate flows for ASIC backend library quality check, maintain and release methodology.
Build and validate flows for design level lib cells usage auditing.
Setup flows/methodology on library in deep submicron physical effects such as aging, self heating, etc.

What We Need To See

MS/PhD in Electrical or Computer Engineering with 2+ years industry experience
Understanding of standard cells/memory/IO/PLL and other hard IP modeling and their usage in the ASIC flow.
Hands-on experience in advanced CMOS technologies, design with FinFET technology 7nm/5nm/3nm and beyond.
Good knowledge with standard cell design & layout
Good knowledge of parameter extraction, device physics, STA methodology and EDA tools.
Understanding spice analysis, crosstalk, electro-migration, noise, OCV, timing margins.
Expertise in coding- TCL, Python, Perl. Familiarity with industry standard ASIC tools: LC, PT, Spice, etc.
Strong communications skill and good teamwork experience

JR2008530