ASIC Design,Verification,DFT Engineer

Company Description Arqonixgen Semiconductor is focused on advancing the next generation of composable data center solutions through high-performance semiconductor products. The company designs scalable, secure, and reliable technologies that enable flexible, software-defined infrastructure for modern workloads. By integrating cutting-edge architectures with robust security and reliability features, Arqonixgen supports data centers that demand high throughput and low latency. Team members collaborate on innovative silicon solutions that power cloud, AI, and enterprise applications in a rapidly evolving industry.
Role Description This is a full-time, on-site role based in Bengaluru for an ASIC Design, Verification, and DFT Engineer. The engineer will be responsible for RTL design and micro-architecture implementation of complex ASIC blocks and subsystems, ensuring alignment with system and performance requirements. Daily work includes developing and executing functional and formal verification plans, writing testbenches, creating assertions, and driving coverage closure. The role involves debugging simulation and silicon issues, collaborating with architecture, physical design, and firmware teams, and contributing to design-for-test strategies such as scan insertion, ATPG pattern development, BIST, and test coverage analysis. The engineer will participate in code reviews, documentation, and continuous improvement of design and verification methodologies and flows.
Qualifications

• Strong RTL Design and Computer Architecture skills, including micro-architecture specification, pipelining, and understanding of memory and interconnect subsystems.
• Hands-on experience with Functional Verification and Formal Verification, including testbench development, constrained-random testing, assertions, and coverage-driven methodologies.
• Proficiency in Debugging complex design and verification issues using simulation, waveform analysis, and hardware debug tools.
• Solid understanding of DFT concepts such as scan, ATPG, BIST, test coverage, and production test flows is highly desirable.
• Experience with industry-standard EDA tools (e.g., Synopsys, Cadence, Mentor) and HDLs such as Verilog/SystemVerilog.
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field, or equivalent practical experience.
• Ability to work collaboratively in cross-functional teams, communicate clearly, and deliver high-quality results under schedule constraints.
• Background in high-performance or data center-class SoCs, networking, or accelerators is a plus.