Key Skills:
Lint, RTL Design, VHDL, CDC, Memory Interfaces (DDR4/LPDDR4), Ethernet, PCIe,
Roles and Responsibilities:
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Lead the design and implementation of complex ASIC products, ensuring high-quality RTL design and verification.
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Oversee the technical team, providing mentorship and guidance to junior engineers.
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Manage the design closure process, ensuring adherence to timelines and quality standards.
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Implement and verify complex protocols, including PCIe, Ethernet, and memory interfaces.
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Conduct static timing analysis and utilize Lint and CDC techniques to ensure design integrity.
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Present technical content to stakeholders at varying levels of abstraction.
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Collaborate with cross-functional teams to drive project success and innovation.
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Participate in hiring and performance management processes to build a strong technical team.
Skills Required:
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Strong expertise in RTL design, VHDL, and CDC techniques
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Experience with Lint and static timing analysis for ASIC verification
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Knowledge of high-speed protocols: PCIe, Ethernet, DDR4/LPDDR4 memory interfaces
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Leadership and mentoring experience for technical teams
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Ability to drive design closure, meet timelines, and maintain high-quality standards
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Strong collaboration and stakeholder communication skills
Education:
Bachelor's or Master's degree in electrical engineering, Computer Engineering, or a related field with extensive experience (12+ years) in digital ASIC/SoC design.