Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.

We are seeking a highly skilled Senior ASIC Design Engineer with hands-on experience in RTL to netlist flows, including RTL Lint, CDC analysis, timing constraints generation, synthesis, and static timing analysis. The role will require front end exposure to evaluate floorplan options, developing constraints, working closely with RTL design teams to run physical aware synthesis flows and providing feedback on area, power, and timing. It also requires working closely with the PD teams to drive P&R closure, understanding congestion, timing feedback, and implementing fixes in RTL. Strong knowledge of clocking, timing and STA signoff closure is required.

Key Responsibilities:

• Work with tool vendors to setup and configure physically aware synthesis flows
• Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.
• Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.
• Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities.
• Perform RTL Lint and work with the RTL designers to create waivers.
• Perform Clock Domain Crossing and Reset Domain Crossing checks and work with the designers to analyze and fix issues
• Develop Timing Constraints for RTL-Synthesis and STA for the blocks and the top-level including SOC. Analyze timing and develop fixes, come up with IO constraints and budgeting.
• Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power).
• Develop flows and metrics for checking RTL quality for PD handoff releases

Minimum Qualifications:

• B.S. or M.S. degree in Computer Engineering, Computer Science, or Electrical Engineering
• 10+ years of experience in Front-End Implementation, synthesis and timing
• Experience with RTL design using SystemVerilog or other HDL.
• Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues.
• Experience with EDA tools and scripting languages (Python, TCL) used to build tools and flows for complex environments.
• Knowledge of standard cell/SRAM memory modeling and timing characterization
• Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools.
• Experience with communicating across functional internal teams and vendors.
• Working knowledge of DFT flows is a plus

Preferred Qualifications:

• Knowledge of Ethernet architecture and networking protocols.
• Experience with physically aware synthesis flows and physical design feedback loops.
• Prior experience with NoC, crossbar designs, or Ethernet switch/host adapter ASICs.
• Working knowledge of DFT flows and methodologies.
• 10+ years of experience managing multiple design releases and collaborating with cross-functional teams.

Location: This is a remote position for employees residing within the United States.

We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.

At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.

In addition to your base pay, you’ll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.