ASIC Design Engineer （2026届）
格兰菲智能科技有限公司 ↗
📍 Wuhan, China 🇨🇳
full-time
mid-level
Expired
Posted —
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Key Skills
ASICVerilogSystemVerilogUVMEDA
Industry
SemiconductorConsumer Electronics
Job Description
该职位来源于猎聘 【职责】
- Develop advanced Computer Graphics Processor System
- Perform RTL design and verification -- including RTL coding, module/system level simulation, coverage analysis and improvement;
- Timing, Performance, Power, Area analysis and improvement, completion of signoff tasks according to the signoff checklists;
- DC/DFT/STA/FV. 【要求】
- BS in CS/EE/ME, Familiar with ASIC design and verification flows.
- Familiar with design/verification languages such as Verilog or SystemVerilog, knowledge of UVM is preferred.
- Hands on experience of EDA tools such as Xcelium or VCS/Verdi is a plus.
- Knowledge of script language such as Makefile, TCL, shell, Python, Perl is desired.
- Good English reading/writing and communication skills.
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Key Skills
ASICVerilogSystemVerilogUVMEDA
Industry
SemiconductorConsumer Electronics
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