rtl design engineer

RTL Design Engineer

Key Responsibilities

• Analyze architectural specifications and define detailed microarchitecture for digital design blocks.
• Develop synthesizable RTL using Verilog/SystemVerilog for IPs, subsystems, and SoC components.
• Create and maintain design documentation, including microarchitecture specifications, interface definitions, and implementation guidelines.
• Collaborate with architecture teams to evaluate design trade-offs and optimize solutions for performance, power, and area (PPA).
• Perform RTL quality checks, including:
• Lint analysis
• CDC (Clock Domain Crossing) checks
• RDC (Reset Domain Crossing) checks
• Synthesis and design rule compliance reviews
• Support functional verification teams by reviewing test plans, debugging simulation failures, and resolving design issues.
• Work closely with RTL integration teams to ensure proper subsystem and SoC-level integration.
• Support synthesis, timing analysis, and physical design teams in achieving timing and implementation closure.
• Analyze and debug functional, timing, and silicon-related issues during pre-silicon and post-silicon phases.
• Participate in design reviews and ensure compliance with coding standards and development methodologies.
• Contribute to low-power design implementation and power optimization techniques.
• Develop reusable design methodologies, scripts, and automation to improve productivity and design quality.
• Support tapeout activities and provide engineering support through silicon bring-up and validation.

Required Skills & Experience

• Strong experience in RTL design using Verilog/SystemVerilog.
• Solid understanding of digital design fundamentals, computer architecture, and SoC design concepts.
• Experience in microarchitecture development and RTL implementation.
• Knowledge of AMBA protocols (AXI, AHB, APB) and standard on-chip interconnects.
• Familiarity with lint, CDC, RDC, synthesis, and static timing analysis flows.
• Understanding of low-power design techniques, clock gating, reset architecture, and power intent methodologies.
• Experience with EDA tools for simulation, synthesis, and RTL quality analysis.
• Strong debugging and problem-solving skills.
• Ability to work effectively in cross-functional teams and manage multiple tasks in a fast-paced development environment.