Skills:
UVM, Design Verification, Soc verification, IP Verification, Subsystem, Functional Verification,
Exp: 5+ Years
Job Description
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Extensive experience in IP/SOC Verification.
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Proficiency in System Verilog and UVM.
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Hands-on experience in verifying IP protocols such as PCIe, DDR, USB, Ethernet, CXL, HDMI, MIPI, DSI, CS, GLS, CPU Verification, or other high-speed protocols.
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Familiarity with scripting languages like Python, Perl, TCL, etc.
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Experience in assembly language or C is a plus.
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Ability to develop testbenches from scratch and take ownership of the entire verification process, including subsystem/chip-level coverage.
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Strong debugging skills.
Key Responsibilities
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Develop testbench components (Driver, Monitor, Scoreboard) from scratch or enhance existing ones for IP, Subsystem, or SOC verification.
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Understand design specifications to define the verification strategy.
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Create testbench micro-architecture, test plans, and coverage plan documents.
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Define verification scope, develop test plans, tests, and verification infrastructure to ensure design correctness.
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Implement SystemVerilog assertions and functional coverage.
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Analyze code coverage and address missing scenarios to meet coverage goals.
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Collaborate with verification team members to develop, execute, and analyze test cases and sequences.
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Work closely with architects, designers, and pre- and post-silicon verification teams to meet deadlines.
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Coordinate with customer leads, ensuring all deliverables and timelines are met.
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Serve as the project's point of contact, responsible for verification signoff.
If you or someone in your network is interested, please apply here or directly reach me on
[email protected]
Looking forward to your response.