Sr. ASIC Designer资深芯片设计工程师

该职位来源于猎聘 Responsibilities: -Chip micro-architecture design and Verilog RTL design for high-performance storage products. -Participate in complete ASIC design flow, including SoC architecture design, implementation, verification, synthesis, and chip bring-up. -Work with SoC architects and firmware engineers to explore new architecture and to optimize system design. -Prepare detailed design specifications of sub-blocks for the next generation NAND flash controller -Design and build block-level test benches to perform block-level verification, and ensure the correctness of the desired functional blocks -Perform design integration, logic synthesis, and design optimization for timing, area and power for given function blocks or sub-systems for data storage applications -Analyze and resolve issues with verification, firmware and validation team. Job Requirements: -B.S. or above in EE/CE/CS or related engineering discipline with 3+ years ASIC design experience. -Hands-on experience in digital circuit design and implementation. Proficient in Verilog/System Verilog coding. Familiar with at least one of script languages, e.g. shell/tcl/perl/makefile/python. -Solid knowledge of ECC algorithm, such as LDPC, BCH etc.is preferred. -Solid knowledge of encryption/decryption algorithm, such as AES, SM4 etc.is preferred. -Solid knowledge of NAND interface protocols, such as ONFI, TOGGLE etc.is preferred. -Experience of SSD storage controller development is preferred. -Knowledge of synthesis (DC), STA, Formal check, CDC flow is a plus. -Self-motivation, teamwork and good communication skills are essential. -Proficient in both written and verbal English. -Knowledge of UVM is a plus. 资深数字芯片设计工程师 工作职责： -负责高性能存储类芯片微架构设计和Verilog RTL设计； -参与芯片设计的整个流程，芯片架构设计实现，并解决验证，综合和芯片调试中发现的设计问题； -与芯片架构师，固件工程师合作，实现新一代芯片架构设计及软硬件调试； -参与下一代SSD主控芯片关键模块的功能制定与设计，撰写完整的设计规格文档 -设计并开发基于模块化的测试脚本和环境，并对所负责的模块进行功能测试与验证，确保子模块的设计正确性 -参与SOC芯片的后端集成，对负责的子模块进行逻辑综合，时序分析，并持续优化时序，面积和功耗，确保整体的SOC芯片设计 -与验证团队，固件开发团队和测试团队合作，分析和解决产品中的问题。 岗位要求： -电子工程、通讯、微电子或相关专业本科及以上，有3年以上工作经验; -熟悉或精通ASIC设计全流程 -精通各种数字设计技能、Verilog/System Verilog设计语言。了解一种或几种脚本语言，如shell/tcl/perl/make/python等； -熟悉LDPC BCH等纠错算法优先； -熟悉AES SM4等加解密算法优先； -熟悉ONFI TOGGLE等NAND接口协议优先； -有SSD Controller控制器领域设计经验者优先； -熟悉综合（DC），STA，Formal Check，CDC设计流程者优先； -具有较强的责任感，学习能力和团队合作能力； -具备中英文读写能力和良好的沟通能力。