SoC RTL DFT Design Engineer

BOS Semiconductors โ†—

๐Ÿ“ Seongnam, Gyeonggi, South Korea, South Korea ๐Ÿ‡ฐ๐Ÿ‡ท

full-time
mid-level
Posted โ€”

Key Skills

DFTSoCRTLASICEagle

Industry

SemiconductorAutomotive

Job Description

โ–ก ํšŒ์‚ฌ ์†Œ๊ฐœ

- ๋ณด์Šค๋ฐ˜๋„์ฒด(BOS Semiconductors)๋Š” ์ฐจ๋Ÿ‰์šฉ ์ž์œจ์ฃผํ–‰ ๋ฐ ์ธํฌํ…Œ์ธ๋จผํŠธ ์‹œ์Šคํ…œ์„ ์œ„ํ•œ

๊ณ ์„ฑ๋Šฅ ๋ฐ˜๋„์ฒด ๋ฐ AI ๊ฐ€์†๊ธฐ ๋ฐ˜๋„์ฒด๋ฅผ ๊ฐœ๋ฐœํ•˜๋Š” ํŒน๋ฆฌ์Šค ๊ธฐ์—…์œผ๋กœ, ์ž๋™์ฐจ๋ฅผ ์ฃผ์š” ํƒ€๊นƒ ์‹œ์žฅ์œผ๋กœ ํ•˜๋ฉฐ

๋™์ผํ•œ ์ œํ’ˆ ํ”Œ๋žซํผ์„ ๊ธฐ๋ฐ˜์œผ๋กœ ๋กœ๋ด‡ ๋“ฑ ๋‹ค๋ฅธ Physical AI ์‹œ์žฅ์œผ๋กœ์˜ ํ™•์žฅ์„ ์ถ”์ง„ํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค.

- ๋Œ€ํ‘œ ์ œํ’ˆ์ธ Eagle-N (AI ๊ฐ€์†๊ธฐ)๊ณผ Eagle-A (์ฐจ๋Ÿ‰์šฉ SoC)๋Š” ์นฉ๋ › ๊ธฐ๋ฐ˜ ํ™•์žฅ์„ฑ๊ณผ

์„ ๋‹จ ๊ณต์ • ๊ธฐ์ˆ ์„ ๋ฐ”ํƒ•์œผ๋กœ ์ฐจ์„ธ๋Œ€ ์ฐจ๋Ÿ‰ ์ „์žฅ ๋ฐ ์ง€๋Šฅํ˜• ์‹œ์Šคํ…œ์— ์ตœ์ ํ™”๋œ ์„ฑ๋Šฅ๊ณผ ์ „๋ ฅ ํšจ์œจ์„ ์ œ๊ณตํ•ฉ๋‹ˆ๋‹ค.

- ์ฐฝ์—… 5๋…„ ์ฐจ์ธ ๋ณด์Šค๋ฐ˜๋„์ฒด๋Š” 300๋ช… ์ด์ƒ์˜ ์—ฐ๊ตฌ๊ฐœ๋ฐœ์ธ๋ ฅ๊ณผ ๋ฒ ํŠธ๋‚จR&D ๋ฒ•์ธ์„ ๊ธฐ๋ฐ˜์œผ๋กœ,

์ฐจ๋Ÿ‰์šฉ ๊ณ ์„ฑ๋Šฅ ๋ฐ˜๋„์ฒด๋ฅผ ์ž์ฒด ๊ฐœ๋ฐœํ•˜์—ฌ ์ƒ˜ํ”Œ ์ถœ์‹œ๊นŒ์ง€ ์„ฑ๊ณต์ ์œผ๋กœ ๋งˆ์ณค์œผ๋ฉฐ ๊ณ„์†ํ•ด์„œ ๋น ๋ฅด๊ฒŒ

์„ฑ์žฅํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค. Global Top ๊ธฐ์ˆ ๋ ฅ์„ ๊ฐ€์ง„ ๊ธฐ์—…๋“ค๊ณผ ๊ฒฝ์Ÿํ•˜๋ฉฐ ์˜๋ฏธ ์žˆ๋Š” ์„ฑ์žฅ์„ ํ•จ๊ป˜

๋งŒ๋“ค์–ด๊ฐˆ ์ธ์žฌ๋ฅผ ๋ชจ์ง‘ํ•ฉ๋‹ˆ๋‹ค.

โ–ก ์กฐ์ง ๋ฐ ์—…๋ฌด ์†Œ๊ฐœ

- ๋ณด์Šค๋ฐ˜๋„์ฒด์˜ DFT(Design-for-Testability)ํŒŒํŠธ๋Š” Automotiveํ–ฅ SoC ์ œํ’ˆ์˜ ํšจ๊ณผ์ ์ธ ์–‘๋ถˆ๋Ÿ‰

์„ ๋ณ„ ํ…Œ์ŠคํŠธ์™€ ๊ณ ์‹ ๋ขฐ์„ฑ ๊ธฐ๋Šฅ ๊ตฌํ˜„์„ ์œ„ํ•œ on-chip HW ๊ตฌ์กฐ์˜ ์„ค๊ณ„์™€ ๊ฒ€์ฆ, ์ œํ’ˆ์˜ ์„ฑ๊ณต์ ์ธ

์–‘์‚ฐ์„ ์œ„ํ•œ DFT ํ…Œ์ŠคํŠธ ํŒจํ„ด ์…‹์—…, ์‹ค๋ฆฌ์ฝ˜ ๋””๋ฒ„๊น…๊ณผ ๋ถ„์„์„ ์ฃผ์š” ์—…๋ฌด๋กœ ํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค.

- ์—…๊ณ„ ์ตœ์‹ ์˜ logic scan compression, logic/memory BIST, boundary scan, in-system test ๊ธฐ๋Šฅ์„

์ œํ’ˆ ์ŠคํŽ™์— ๋งž์ถ”์–ด ์ตœ์ ํ™”ํ•˜๋ฉฐ, IP/SoC ์„ค๊ณ„ํŒ€, Physical Implementation ํŒ€๊ณผ์˜ ๊ธด๋ฐ€ํ•œ ํ˜‘๋ ฅ์„

ํ†ตํ•˜์—ฌ ISO 26262 ํ‘œ์ค€ ์š”๊ฑด์„ ์ถฉ์กฑํ•˜๋Š” ์—…๋ฌด ์™„๊ฒฐ์„ฑ๊ณผ coverage์˜ ๋‹ฌ์„ฑ์ด ํŒ€์˜ ๋ฏธ์…˜์ž…๋‹ˆ๋‹ค.

โ–ก ์ฃผ์š” ์—…๋ฌด

- Automotive SoC ๋‚ด๋ถ€ logic, embedded SRAM์„ ์œ„ํ•œ test, repair logic์˜ ์ƒ์„ฑ๊ณผ ์‚ฝ์ž…, ๊ฒ€์ฆ

- Test cost ๊ฐ์†Œ๋ฅผ ์œ„ํ•œ IP, block, full-chip DFT ๊ตฌ์กฐ ์ตœ์ ํ™”์™€ ๊ฒ€์ฆ

- Si. bring-up๊ณผ ์–‘์‚ฐ ATE ๋ฒกํ„ฐ ์ƒ์„ฑ๊ณผ ๊ฒ€์ฆ

- ๊ณ ์‹ ๋ขฐ์„ฑ ๊ธฐ๋Šฅ ๊ตฌํ˜„์„ ์œ„ํ•œ ํ…Œ์ŠคํŠธ H/W ๋กœ์ง ๊ฐœ๋ฐœ๊ณผ ๊ตฌํ˜„

โ–ก ํ•„์š” ์—ญ๋Ÿ‰

[๊ฒฝ๋ ฅ 5๋…„ ์ดํ•˜]

- ์ „๊ธฐ์ „์ž, ์ปดํ“จํ„ฐ ๊ด€๋ จ ์ „๊ณต ํ•™์‚ฌ ์ด์ƒ

- EDA tool (Synopsys, Siemens, Cadence) ๊ธฐ๋ฐ˜์˜ ASIC Front-End/DFT ๊ตฌํ˜„

- RTL2GDS flow์— ๋Œ€ํ•œ ์ „๋ฐ˜์ ์ธ ์ดํ•ด์™€ ์‹ค๋ฌด ๊ฒฝํ—˜

- Testability, Scan/MBIST/LBIST๋“ฑ์˜ DFT ๊ด€๋ จ ๊ธฐ์ˆ ์˜ ์ดํ•ด

- ํ•ด์™ธ ์—ฌํ–‰์— ๊ฒฐ๊ฒฉ ์‚ฌ์œ ๊ฐ€ ์—†์œผ์‹  ๋ถ„

[๊ฒฝ๋ ฅ 6๋…„ ์ด์ƒ]

- SoC ์ œํ’ˆ full-chip DFT ๊ตฌํ˜„๊ณผ sign-off, TO ๊ฒฝํ—˜

- SoC ์ œํ’ˆ DFT si. bring-up, diagnosis ๊ฒฝํ—˜

- Full-chip flatten/HPDF Synthesis, DFT, STA ์‹ค๋ฌด ๊ฐ€๋Šฅ์ž

- Foundation-IP, PHY/AMS IP integration ์œ ๊ฒฝํ—˜์ž

- ํ•ด์™ธ ์—ฌํ–‰์— ๊ฒฐ๊ฒฉ ์‚ฌ์œ ๊ฐ€ ์—†์œผ์‹  ๋ถ„

โ–ก ์šฐ๋Œ€ ์‚ฌํ•ญ

- Automotive SoC, NPU accelerator ๊ณผ์ œ ์œ ๊ฒฝํ—˜์ž(DFT, RTL2GDS)

Key Skills

DFTSoCRTLASICEagle

Industry

SemiconductorAutomotive

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BOS Semiconductors
Seongnam, Gyeonggi, South Korea, South Korea