SoC Design Verification Engineer

SoC Design Verification Engineer

Location: San Jose, CA

Duration: Full-time

Customer – LTTS/Etched

Please do not apply if you can’t take calls

Key Responsibilities:

• Develop and execute SoC-level validation and performance verification strategy
• Build system-level testbenches, workloads, and performance models
• Analyze performance bottlenecks across CPU, memory, interconnect, and accelerators
• Perform power and performance trade-off analysis
• Collaborate with architecture, RTL, and software teams
• Debug issues at system level (HW + FW/SW interaction)

Required Skills:

• Strong experience in SoC-level DV / Performance validation
• Understanding of CPU architecture, memory hierarchy, NoC/interconnect
• Expertise in SystemVerilog/UVM + C/C++/Python
• Experience with performance profiling tools
• Strong debugging and analytical skills

Good to Have:

• Experience in post-silicon validation / bring-up
• Knowledge of AI/ML or high-performance computing workload