SoC Design Engineer

OMNIVISION 

📍 Santa Clara, United States 🇺🇸

full-time
mid-level
151091
Expired
Posted —
This job posting has expired View All SoC Design Engineer Jobs

Key Skills

RTLVLSISystemVerilogPythonCMOS

Industry

SemiconductorConsumer Electronics

Job Description

Description

  • B e responsible for digital design of image sensor, SoC integration and IP design, analysis, integration, and validation.
  • Work closely with back-end team in floor-planning, timing closure and DFT.
  • Conduct image sensor array/analog related timing control design and STA.
  • Perform chip bring-up, validation and debugging.
  • Design, integrate and validate ISP data pipes according to PRD/design specification and system architecture of SoC CIS products, following ASIC design flow.
  • Coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages.
  • Work on enhancing the functionality of the grp_holdip.
  • Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS .
  • Work with sensor digital and analog engineers for system design, integration and validation.
  • Work with algorithm engineers for module level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co-simulation.
  • Work with algorithm and application engineers for image tuning and qualification.
  • Conduct silicon validation, debugging and tuning.

Job Requirements

Master’s degree in Electrical Engineering, Computer Engineering or related fields with the course work of Digital System Design , MOS VLSI Circuit Design , Asynchronous VLSI Design , Computer Systems Architecture and Organization , and Network Processor Design and Programming.

Required Skills

  • Digital simulator and waveform viewer.
  • RTL Design/coding, Verification, Simulation and debugging.
  • CMOS and/or VLSI design
  • Circuit design and simulation.
  • Verification language: System Verilog, Verilog.
  • CPU microarchitecture (out-of-order execution, register renaming, reservation stations, processor pipelines.)
  • Computer architecture: out-of-order execution, data hazard, cache/memory, subsystems, cache hierarchy design.
  • Python, Assembly, Shell and Perl Script programming.
  • Using Linux and Source control system.

Annual base salary for this role in California, US is expected to be between $151,091- $155,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.