We are seeking a Senior SoC Design and Integration Engineer to drive the design, integration, and implementation of SoCs, focusing on high-speed interconnects, IP integration, and ASIC execution. This role involves configuring, integrating, and supporting IP verification, including RTL design, synthesis, and working with the physical design team for timing closure. Responsibilities include integrating UCIe or similar high-speed IPs into SoC designs, defining and configuring AXI-based NoCs, acting as a technical liaison between IP vendors and various teams, running synthesis and design checks, optimizing RTL integration for power, performance, and area, collaborating with physical design and verification teams, debugging design and timing issues, supporting post-silicon validation, and supporting emulation and FPGA-based prototyping. The candidate should have strong problem-solving skills, excellent communication, and at least 10 years of experience in ASIC/SoC design, integration, and implementation. Technical expertise required includes RTL design and integration (Verilog/SystemVerilog), interconnect protocols like AXI, high-speed interfaces (UCIe, CXL, PCIe, DDR), logic synthesis, static timing analysis, low-power design, EDA tools, physical design constraints, formal verification, pre-silicon verification, post-silicon bring-up, and programming/scripting in Tcl/Python. Preferred qualifications include experience with UCIe/CXL/PCIe/Serdes. The position is located in Santa Clara, CA or Orange County, CA, with a competitive compensation package including base salary, bonus, and equity, plus benefits.