Key Skills
RTLVerilogMIPIDDREDA
Industry
SemiconductorAutomotive
Job Description
About This Job
ACL Digital
Location: Bengaluru, Karnataka, India
Work Mode: On-site
Industry: IT Services and IT Consulting
Job Description
Job Title: Senior RTL Design Engineer (ASIC/SoC)
(with DDR/LPDDR/MIPI exp)
Location: Bangalore, Indi
aExperience: 4+ Year
sNotice Period: 30–45 Days (Preferred
)
Role Overvie
w:We are looking for a highly skilled and motivated ASIC RTL Design Engineer to join our team in Bangalore. You will be responsible for the microarchitecture, design, and implementation of complex digital IP blocks and subsystems. The ideal candidate will have strong expertise in high-speed interface protocols and a proven track record of delivering high-quality RTL within the ASIC/SoC design flo
w.
Key Responsibilit
iesMicroarchitecture DefinitionRTL ImplementationProtocol Expertise: DDR/LPDDR and MIPI protocols.Design Quality: Perform RTL quality checks, including Linting, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) analysis.Timing Clos
ure
Mandatory Skills & Experi
enceExperience: 4+ years of hands-on industry experience in ASIC RTL design.Domain Expertise: Deep knowledge of DDR/LPDDR memory controllers and/or MIPI (C-PHY/D-PHY) interface design.Languages: Expert-level proficiency in Verilog/SystemVerilog.Design Flow: Strong understanding of the ASIC design flow: RTL to Synthesis/STA.Tools: Hands-on experience with industry-standard EDA tools (e.g., Synopsys Design Compiler, SpyGlass, or equivalent).Communication: Excellent analytical, problem-solving, and collaboration skills for working in a fast-paced environm
ent.
Good to
HaveExperience with low-power design techniques (Clock gating, Power gating, UPF).Proficiency in scripting languages (Python, Perl, or Tcl) for design automation.Familiarity with on-chip interconnect protocols (e.g., AMBA AXI/AHB).Prior experience with silicon bring-up and d
ebug.
ACL Digital
Location: Bengaluru, Karnataka, India
Work Mode: On-site
Industry: IT Services and IT Consulting
Job Description
Job Title: Senior RTL Design Engineer (ASIC/SoC)
(with DDR/LPDDR/MIPI exp)
Location: Bangalore, Indi
aExperience: 4+ Year
sNotice Period: 30–45 Days (Preferred
)
Role Overvie
w:We are looking for a highly skilled and motivated ASIC RTL Design Engineer to join our team in Bangalore. You will be responsible for the microarchitecture, design, and implementation of complex digital IP blocks and subsystems. The ideal candidate will have strong expertise in high-speed interface protocols and a proven track record of delivering high-quality RTL within the ASIC/SoC design flo
w.
Key Responsibilit
iesMicroarchitecture DefinitionRTL ImplementationProtocol Expertise: DDR/LPDDR and MIPI protocols.Design Quality: Perform RTL quality checks, including Linting, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) analysis.Timing Clos
ure
Mandatory Skills & Experi
enceExperience: 4+ years of hands-on industry experience in ASIC RTL design.Domain Expertise: Deep knowledge of DDR/LPDDR memory controllers and/or MIPI (C-PHY/D-PHY) interface design.Languages: Expert-level proficiency in Verilog/SystemVerilog.Design Flow: Strong understanding of the ASIC design flow: RTL to Synthesis/STA.Tools: Hands-on experience with industry-standard EDA tools (e.g., Synopsys Design Compiler, SpyGlass, or equivalent).Communication: Excellent analytical, problem-solving, and collaboration skills for working in a fast-paced environm
ent.
Good to
HaveExperience with low-power design techniques (Clock gating, Power gating, UPF).Proficiency in scripting languages (Python, Perl, or Tcl) for design automation.Familiarity with on-chip interconnect protocols (e.g., AMBA AXI/AHB).Prior experience with silicon bring-up and d
ebug.
Featured Opportunities
Key Skills
RTLVerilogMIPIDDREDA
Industry
SemiconductorAutomotive
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