Senior RTL Design Engineer – SoC Infrastructure

We are developing a high-performance multi-core vector processor with a custom ISA and are looking for an experienced RTL Design Engineer to implement and integrate critical SoC infrastructure blocks.

• DDR4 memory controller integration with vendor PHY IP.
• Flash boot engine integration.
• Security subsystem implementation including Secure Boot, Root of Trust, Key Management, and Lifecycle Management.
• IEEE 1149.1 (JTAG) debug controller implementation.
• Trace aggregation and debug infrastructure development.
• PLL, clock/reset, and clock gating implementation.
• Integration of third-party IPs including DDR PHY, SerDes PHY, and PLL.
• Development of custom RTL wrapper modules for SoC integration.

• 5–8 years of hands-on ASIC/SoC RTL design experience.
• Strong SystemVerilog RTL design expertise.
• DDR3/DDR4 memory controller and PHY integration experience.
• Hardware security implementation experience.
• IEEE 1149.1 (JTAG) implementation.
• Vendor IP integration in complex SoCs.
• Clock/reset architecture and PLL integration.

• HMAC-SHA256 or cryptographic hardware.
• Trace and debug infrastructure.
• Anti-tamper and anti-rollback mechanisms.
• BIST and Scan/DFT experience.

• Experience in CPU, AI Accelerator, Networking, HPC, or Custom SoC projects.
• Strong RTL development and SoC integration skills.
• Ability to independently own design blocks from specification to integration.

If you meet the above requirements and are interested in this opportunity, please apply through LinkedIn or share your updated resume for a referral review .

📧 Email: [email protected]

Note: Please mention "Senior RTL Design Engineer – Bengaluru" in the email subject line.

Candidates with 5–8 years of relevant ASIC/SoC RTL design experience and immediate to 30-day availability are encouraged to apply.



This role requires a minimum of 5 years of relevant ASIC/SoC RTL design experience.

Immediate to 30-day joiners are preferred.

Candidates with only academic projects, internships, or unrelated RTL/FPGA experience are requested not to apply.