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Senior RTL Design Engineer, Core IP, Silicon

📌Bengaluru, India 🇮🇳

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⏱︎ full-time

🧙‍♂️ senior

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  • 10 years of work experience in RTL design.
  • Experience with ASIC design methodologies for clock domain checks and reset checks.
  • Experience in RTL coding using System Verilog/Verilog.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering or Computer Science.
  • Experience in area, power and performance design optimization.
  • Experience implementing Machine Learning Accelerators, Camera ISP image processing IP, or other multimedia IPs such as Display or Video Codec.
  • Experience in scripting languages, C/C++ programming and software design skills.

About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.

Responsibilities

  • Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top-level integration.
  • Define and develop Register-Transfer Level (RTL) implementations that meet engaged power, performance and area goals.
  • Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up.
  • Participate in test plan and coverage analysis of the sub-system and chip-level verification.
  • Create tools/scripts to automate tasks and track progress. Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning.


Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
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