Senior Lead RTL Design Engineer

Company Description:

MosChip® Technologies is a publicly traded company specializing in silicon and product engineering solutions, with a team of over 1300 engineers across Silicon Valley, USA, and India. The company delivers end-to-end engineering services, including silicon design and verification, systems and software engineering, device engineering, multimedia, mobility, connectivity, AI/ML solution design, and test automation.

MosChip® also focuses on developing Digital IPs, Verification IPs, Mixed Signal IPs, and providing Turnkey ASIC services. The organization has shipped millions of connectivity ICs and has a strong record of over 200 successful SoC tape-outs with first-time-right silicon. This depth of expertise offers engineering professionals the opportunity to work on complex, high-impact semiconductor projects.

Role Description:

The Senior Lead RTL Design Engineer is a full-time, on-site role based in Hyderabad and Bangalore. The role involves leading RTL design activities for complex SoCs and IP blocks, including architecture review, micro-architecture development, and implementation in hardware description languages. Responsibilities include collaborating with verification, physical design, and firmware teams to ensure design quality, performance, and timing closure, as well as participating in design reviews and resolving technical issues.

The engineer will oversee integration of IPs, manage design documentation, and support implementation flows such as synthesis, static timing analysis, and formal checks. Day-to-day tasks also include mentoring junior engineers, driving best practices in design methodology, and contributing to continuous improvement across projects.

Qualifications:

ASIC RTL /SOC Design/IP Design :

General knowledge how things work in RTL team and be able to handle basic-to-mid level RTL tasks:

• RTL design /release flows/infra (LINT, CDC, UPF, IPXACT, CSR …)
• Good working knowledge in general scripting (Perl, Python, Make ...)
• Customer methodology/flow ask and complaints. Should be able to take up infra cleanup. Some good examples of infra cleanup:
• Correctly clean PERL warnings during RTL build to find/fix any poor usage of variables
• Own automated tools driven regressions runs of available tools in alternate modes for RTL -focused builds
• VCS compiles with selective, not global-ignore, lint and warning bars on just ckt models, hardIP blocks stand-alone, full RTL -only PHY
• Cleanup of grep or other bars to prevent bad `ifdef usage, naming conventions (extend spyglass or add our own), etc.
• Creating design build configurations for different modes like ATPG, HWEMUL

Locations:

• Hyderabad and Bangalore.

Duration:

• Full time/Permanent