Senior FPGA Emulation Engineer

Job Summary

We are seeking an experienced Emulation & FPGA Prototyping Engineer to support pre-silicon validation, system-level debug, and hardware/software co-verification of complex SoC designs.The ideal candidate will have strong expertise in RTL integration, FPGA-based emulation flows, timing closure, and debugging high-speed interfaces using industry-standard tools such as HAPS, ProtoCompiler, VCS, Verdi, PrimeTime, and Vivado.

Key Responsibilities

FPGA Prototyping & Emulation

• Build and maintain FPGA-based prototypes using HAPS or similar platforms.
• Convert RTL drops into synthesizable and partitioned multi-FPGA builds (ProtoCompiler / Vivado / Quartus).
• Generate bitfiles, perform bring-up, and validate system functionality on FPGA hardware.
• Integrate Hybrid VCS / Simics models for mixed simulation/emulation environments.
• Work closely with software teams to enable early firmware, BIOS, and driver testing.

RTL Integration & Verification

• Integrate and debug RTL modules, SOC blocks, and VIP in SystemVerilog/Verilog.
• Run simulations using VCS and debug issues via Verdi or waveform tools.
• Develop and maintain testbenches, checkers, and validation flows.

Timing Analysis & Closure

• Create and optimize FPGA timing constraints (SDC/TCL).
• Debug timing violations in Vivado/Quartus/ProtoCompiler.
• Translate ASIC timing constraints (PrimeTime) to FPGA constraints.
• High-Speed Interface Debug

Validate and debug interfaces such as:

• PCIe Gen1–5
• CXL
• USB
• DDR4/DDR5
• Work with protocol VIPs and test sequences to ensure compliance.

Automation & Scripting

• Develop automation flows using TCL, Perl, Python, Makefile.
• Create regression environments and dashboards for build/test status.
• Automate metrics extraction, reports, and validation logs.

Required Technical Skills

• Strong knowledge of SystemVerilog / Verilog
• Experience with FPGA tools: HAPS, ProtoCompiler, Vivado, Quartus
• ASIC simulation tools: VCS, Verdi, Simics (plus point)
• Timing tools: PrimeTime, NanoTime, SDC constraints
• Strong scripting: TCL, Perl, Python, Shell
• Understanding of SOC architecture, clock/reset design, and CDC concepts
• Debugging experience with PCIe, CXL, USB, DDR (preferred)

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
• 5–20+ years of experience in FPGA prototyping, emulation, SoC validation, or similar fields
• Strong analytical and debugging skills
• Experience working in cross-functional hardware + software teams

Nice to Have

• Experience with Synopsys Verification / Emulation tools
• Knowledge of physical design timing, STA, ECO flows
• Experience with UVM or advanced verification methodologies
• Background in EDA tool support or methodology development