Senior ASIC RTL Design Engineer

MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.

Required Skills

• Experience in Logic design / RTL coding is a must.
• Experience is SoC design and integration for complex SoCs is a must.
• Experience in Verilog/System-Verilog is a must.
• Experience in Multi Clock designs, Asynchronous interface is a must.
• Experience in using the tools in ASIC development such as Lint and CDC.
• Experience in Synthesis / Understanding of timing concepts is a plus.
• Experience in ECO fixes and formal verification.
• Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
• Excellent oral and written communications skills.
• Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

Education Requirements:

B. Tech / M. Tech (ECE)

Experience: 5 to 12 Years

Location: Hyderabad/Bangalore