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Saransh

Senior ASIC RTL Design Engineer - W2 Role - 100% Remote

Saransh

📍 United States, United States 🇺🇸

contract

senior

remote

Posted —

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Key Skills

SystemVerilogVerilogFPGAASICPython

Industry

SemiconductorConsumer Electronics

Job Description

Role: Senior ASIC RTL Design Engineer

100% Remote (US)

Job Type: W2 Contract

Must Have: BSc/MSc in Electronics, Radio Engineering, Computer Engineering, or related field

About The Role

You will join a digital hardware team and contribute across the full silicon development lifecycle from preliminary analysis and micro-architecture definition through RTL development, functional verification, ASIC/FPGA/SoC implementation, on-hardware bring-up, and design documentation. Engineers are expected to be customer-facing: presenting technical solutions, gathering and documenting requirements, and supporting both PoC and production phases.

Responsibilities

Design synthesizable SystemVerilog/Verilog for high-performance compute subsystems: systolic arrays, vector/tensor datapaths, on-chip memory, DMA engines, and control logic
Translate architecture specifications into PPA-efficient RTL; drive timing closure and deliver clean handoffs to synthesis, physical design, and verification teams
Investigate and implement architectural and microarchitectural power optimizations: clock gating, operand gating, power islands, voltage domains, and datapath activity reduction
Build and refine RTL-level power models; collaborate on power budgeting, measurement correlation, and convergence to chip-wide power goals across pre- and post-silicon milestones
Define and integrate chip-wide power management strategies: DVFS, idle/sleep states, wake sequencing, and coordination with firmware and system thermal policies
Integrate blocks at SoC/top level clock/reset domains, bus fabrics (AXI/CHI/NOC), DFT applying low-power design methodology (lint, CDC/RDC, synthesis constraints)
Partner with architects, physical design, verification, firmware, and compiler/runtime teams on hardware software co-design and ML kernel mapping (GEMM, convolution, attention)
Support FPGA/emulation bring-up and post-silicon debug; analyze waveforms, evaluate power/performance tradeoffs, and propose ECOs under ambiguity
Strong ownership, scripting proficiency (Python/Tcl), and fluency with industry EDA flows (DC/Genus, PrimeTime, VCS/Xcelium, SpyGlass, Verdi)

Core Skills & Qualifications

BSc/MSc in Electronics, Radio Engineering, Computer Engineering, or related field
Solid grounding in digital electronics, logic design, and ASIC/FPGA/SoC fundamentals
Experience taking a design through the full lifecycle on real hardware (FPGA, SoC, or ASIC)