Looking for candidates with experience in
IP Validation, PCB Validation
,
Post-Silicon Validation, SoC Validation, System Validation, or Hardware Validation
related to IPs.
Important:
If a candidate is selected for any one of these four positions, the remaining three submissions for that candidate will be automatically closed.
Experience with different IPs is preferred. Exposure to the following is a plus:
PCIe
UCIe
Ethernet
Signal Integrity (SI)
Strong knowledge of Computer Architecture and SoC Architecture is mandatory.
Hands-on experience with the following is expected:
Logic Analyzer
PCB Debugging
Firmware Validation
Linux
Windows
IP/System-level Bring-up
Experience Requirements:
Level 1:
2–4 years
Level 2:
3–6 years
Candidates with
strong, relevant academic/research experience
but limited or no industry experience may also be considered.
Although the overall acceptable range is
0–10 years
, the Hiring Manager prefers candidates with
10 years or less
, as these are junior-level positions.
Relocation candidates are acceptable.
Minimum Qualification:
Bachelor's degree.
Ideal Candidate Profile
Experience in
Post-Silicon/IP/SoC/System Validation
.
Strong understanding of
Computer Architecture and SoC Architecture
.
Experience with
IP/System bring-up
and hardware debugging.
Proficient in using
Logic Analyzers
and performing
PCB debugging
.
Familiarity with
Linux
,
Windows
, and
Firmware Validation
.
Exposure to
PCIe, UCIe, Ethernet,
or
Signal Integrity
is an added advantage.
Suitable for candidates ranging from
fresh graduates with relevant academic projects
to professionals with
up to 10 years of experience
, with an ideal target of
2–6 years
.