Rtl Digital Design

We are hiring for two project positions in my group, WirelessX Lab, at IIT Dharwad, under a sponsored project funded by the Department of Telecommunications.

1. RTL / Digital Design

We are looking for candidates with a background in ECE / EE / CS and experience or interest in Verilog / SystemVerilog, FPGA implementation, RISC-V architecture, and digital communication systems / signal processing.

2. Hardware / PCB Design

We are looking for candidates with a background in ECE / EE and experience or interest in multi-layer PCB design, high-speed digital design, and RF / microwave layout.

Emolument: ₹37,000 to ₹58,000 per month + HRA as applicable

Application Link:

https://www.jotform.com/220951115443448

Application Deadline:

28 June 2026, 11:59 PM IST

Applications received after the deadline will not be considered for the current round of selection under this project.

Interested and eligible candidates are encouraged to apply.