RTL Design Engineer

LeadIC Design Pvt Ltd is a leading semiconductor engineering company providing end-to-end VLSI design services to global semiconductor and product companies. Founded in 2018, LeadIC has established itself as a trusted engineering partner delivering high-quality Digital Design, Verification, Physical Design, DFT, FPGA Prototyping, and ASIC implementation services.

With engineering teams across India and Canada, we work on cutting-edge semiconductor technologies, enabling customers to build next-generation silicon products.

We are looking for an experienced RTL Design Engineer with 5+ years of experience in RTL design and SoC/IP integration. In this role, you will contribute to the development of a compute-intensive multi-core vector processor featuring a custom ISA. You will be responsible for implementing and integrating key SoC infrastructure blocks, including the memory controller, security subsystem, debug infrastructure, trace unit, and clock/reset unit.

This is a full-time, on-site opportunity based in Bengaluru, Karnataka .

• Integrate DDR4 memory controller with vendor PHY IP and flash boot engine.
• Implement the security subsystem, including secure boot, silicon Root-of-Trust integration, key management, lifecycle state management, and scan chain gating.
• Design and implement the trace aggregation unit supporting multi-source event collection, ring buffer management, filtering, and host readout interfaces.
• Develop IEEE 1149.1 compliant JTAG debug controller, including TAP state machine, debug module interface, and system-wide halt functionality.
• Build clock and reset infrastructure, including PLL configuration, phased reset sequencing, and per-core clock gating.
• Integrate third-party IPs such as DDR PHY, SerDes PHY, and PLLs using custom wrapper modules.
• Collaborate with architecture, verification, DFT, physical design, and firmware teams throughout the SoC development lifecycle.
• Develop high-quality, synthesis-friendly SystemVerilog RTL and support integration, debug, and silicon bring-up activities.

• 5+ years of RTL Design experience using Verilog/SystemVerilog.
• Strong experience with DDR3/DDR4 memory controller integration and vendor PHY IP.
• Experience implementing hardware security features, including secure boot, OTP, key storage, Root of Trust, and lifecycle management.
• Hands-on experience implementing JTAG (IEEE 1149.1) debug infrastructure.
• Experience integrating vendor IP with custom RTL.
• Strong understanding of PLL configuration, clock distribution, reset architecture, and clock gating.
• Experience with RTL integration, synthesis, linting, and timing-aware design methodologies.
• Strong debugging, analytical, and problem-solving skills.
• Excellent communication and collaboration skills.

• Experience implementing HMAC-SHA256 or other cryptographic hash engines.
• Knowledge of ARM CoreSight-like trace and debug infrastructure.
• Experience with anti-tamper and anti-rollback security mechanisms.
• Familiarity with DFT features, including BIST and scan integration.
• Experience working on complex ASIC/SoC development programs.

Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related discipline.

• Work on advanced processor and SoC development projects.
• Exposure to cutting-edge semiconductor technologies.
• Collaborate with highly experienced engineering teams.
• Opportunity to work across the complete ASIC design lifecycle.
• Strong technical learning and career growth opportunities.

• Experience: 5+ Years
• Location: Bengaluru, Karnataka
• Work Mode: On-site
• Employment Type: Full-time
• Notice Period: Immediate Joiners or candidates with a maximum 15-day notice period are preferred.

If you're passionate about designing high-performance SoCs and have expertise in RTL design, memory subsystems, security, and debug infrastructure, we'd love to hear from you.

Interested candidates can share their updated resume at [email protected] or DM me directly. Referrals from your network are also welcome.