RTL Design Engineer

TITLE: RTL DESIGN ENGINEER(Principal/Senior Staff Engineer)

LOCATION: GREATER BENGALURU AREA

Company Description

We are looking for exceptional talent and leadership to join Fast Growing Startup into Scalable Intelligence, the world’s first company developing Agentic Silicon for powering the future of AI.

Founded in 2023, We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.

Job Description

Job Title: Design Engineer (Front-End/RTL)

Role Overview

As a Design Engineer, you will be the bridge between high-level architecture and physical

implementation. You will own the development of critical SoC subsystems/IPs, translating

complex architectural requirements into efficient, high-performance RTL. This role requires

someone who thrives on solving complex design challenges and can maintain design integrity

through the rigors of synthesis, timing, and verification.

Key Responsibilities

- Micro-architectural Definition: Translate high-level architectural requirements into

robust, detailed micro-architectural specifications.

- Design & Implementation: Develop high-quality, synthesizable RTL using Verilog and

SystemVerilog, ensuring designs meet performance, power, and area (PPA) targets.

- Strategic Analysis: Conduct deep-dive analyses of implementation options, weighing

trade-offs between latency, throughput, and silicon real estate.

- Full Front-End Flow: Drive the design through the ASIC front-end suite, including

Synthesis, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC).

- Timing Ownership: Take responsibility for timing closure to ensure the design meets

frequency targets across all corners.

- Cross-Functional Collaboration: Manage design iterations by working closely with the

Verification team and the Physical Design team

- Debugging: Root-cause complex issues across simulation, linting, CDC, and synthesis

environments.

Required Qualifications

Education & Expertise

- Degree: Bachelor’s or Master’s degree in EC/EE/CS or a related field.

- Experience: 5–10 years of proven experience in SoC or Subsystem-level design.

- Good understanding of the AMBA protocols, specifically CHI, AXI, AHB, and APB.

- Expert-level proficiency in Verilog/SystemVerilog and micro-architecture development.

- Hands-on experience with CDC/RDC tools, Linting, and Logic Synthesis (e.g., Design compiler, Genus).

- Strong proficiency in Static Timing Analysis (STA) and timing constraints

- Good understanding of ARM architecture is desirable.

- Strong communication skills to articulate complex technical trade-offs to stakeholders

Contact

Sumit S. B

[email protected]

www.mulyatech.com

"Mining the Knowledge Community"

Practice Head(Talent Acquisition. Semiconductors Domain)