RTL Design Engineer

Job Description:

Key Responsibilities:

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RTL Design & Development: Write and debug synthesizable RTL code using Verilog or SystemVerilog for application-specific integrated circuits (ASICs).

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Static Verification: Execute front-end quality checks, including RTL Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC).

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Synthesis & Optimization: Run logic synthesis to generate optimized gate-level netlists targeting strict constraints for power, area, and timing.

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Cross-functional Collaboration: Work closely with architecture, physical design, and firmware teams to translate high-level specifications into physical silicon.

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Automation: Develop scripting tools (e.g., Python, Perl, Tcl) to automate implementation and testing flows.

Minimum Qualifications:

Education: B.S. or M.S. degree in Computer Science, Electrical Engineering, or a closely related technical field.

Technical Skills: Strong proficiency in SystemVerilog, HDL coding, and knowledge of front-end ASIC design flows.

Verification Experience: Hands-on experience with linting, formal verification, and SoC integration (Reset, PLLs, Clocking).

Communication: Ability to collaborate with multi-functional teams and handle hardware-software interface discussions