RTL Design Engineer

Job Requirements

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

Key Responsibilities

Design and develop static IP blocks using Verilog/SystemVerilog, including architecture exploration, micro-architecture development, memory integration, and ensuring RTL quality through lint, CDC, synthesis, and power optimization flows while meeting stringent timing and area requirements.

• Interface extensively with Design Verification (DV) teams for test plan development and debug activities, collaborate with Physical Design (PD) teams on timing closure, floorplanning, and wrapper-level implementation, and work closely with Design for Test (DFT) teams on MBIST insertion, scan architecture, and testability requirements throughout the project development lifecycle.
• Demonstrate expertise in industry-standard EDA tools including lint/CDC, synthesis tools for power optimization, and physical-aware design methodologies, while developing UPF/SDC collaterals, managing clock domain crossing issues, and ensuring compliance with RTL design guidelines and Static verification requirements.
• Lead end-to-end IP integration activities including soft and hard IP identification/selection, subsystem wrapper generation, NOC interface design, and coordination of complex multi-stage release deliverables (milestones) while maintaining design consistency across SOC's distributed development model with external partners.
• Drive static IP development within the complex SOC architecture supporting AR/VR compute acceleration, manage subsystem delivery requirements across multiple release stages, ensure seamless integration with generated collaterals, and contribute to the project's success through proactive problem-solving and technical leadership in this high-visibility, cutting-edge silicon program.
  
  

Qualifications:

• BS/MS in Electrical Engineering, Computer Engineering, or equivalent experience
• 5+ years of digital design/ASIC development experience
• Strong RTL design fundamentals and SystemVerilog expertise
• Experience with complex SOC integration and cross-functional collaboration
• Knowledge of power optimization, timing closure, and advanced technology nodes
  
  

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.

Qualifications:

Work Experience

• BS/MS in Electrical Engineering, Computer Engineering, or equivalent experience
• 5+ years of digital design/ASIC development experience
• Strong RTL design fundamentals and SystemVerilog expertise
• Experience with complex SOC integration and cross-functional collaboration
• Knowledge of power optimization, timing closure, and advanced technology nodes