RTL Design Engineer

Hiring: RTL Design Engineer

Location: Bay Area, USA

Employment Type: Full-Time

We are looking for an experienced RTL Design Engineer to join a leading semiconductor team working on next-generation ASIC/SoC designs.

Key Responsibilities:

• Design, develop, and debug synthesizable RTL using Verilog/System Verilog for complex ASIC/SoC designs.
• Perform front-end design quality checks, including RTL Lint, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) analysis.
• Execute logic synthesis and optimize designs to meet power, performance, area (PPA), and timing requirements.
• Collaborate with architecture, physical design, verification, and firmware teams to deliver high-quality silicon solutions.
• Develop and maintain automation scripts using Python, Perl, or Tcl to improve design and verification workflows.

Required Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science , or a related discipline.
• Strong experience in RTL design using Verilog/SystemVerilog and frontend ASIC design methodologies.
• Hands-on experience with RTL linting, CDC/RDC analysis, formal verification, and SoC integration .
• Solid understanding of synthesis, timing, reset, clocking, and PLL concepts.
• Excellent problem-solving, communication, and cross-functional collaboration skills.

📩 Interested candidates? Please share your updated resume to [email protected]