Minimum qualifications:

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience
• 3 years of experience designing RTL digital logic using SystemVerilog for ASICs or equivalent experience
• Experience with ASIC design methodologies and QA flows (Lint, CDC, RDC, VCLP)
• Experience with a scripting language such as Perl or Python
  
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science
• 6 years of experience designing RTL digital logic using SystemVerilog for ASICs or equivalent experience
• Experience in area, power and performance design optimization
• Experience in design and development of security or audio blocks
  
  

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

You will be responsible for RTL design development of audio and Security IPs and subsystems. This includes micro architecture, RTL coding, low power design, constraints, IP release flows, PPA optimizations, testplanning collaboration, coverage reviews, and closure for high quality and optimized security designs.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Collaborate with architects and develop microarchitecture.
• Perform Verilog/SystemVerilog RTL coding, functional/performance simulation debug and Lint/CDC/FV/UPF checks.
• Develop RTL implementations that meet competitive power, performance and area targets.
• Participate in synthesis, timing/power closure, and support pre-silicon and post-silicon bring-up.
• Participate in test planning and coverage analysis. Create tools/scripts to automate tasks and track progress.
  
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .