RTL ASIC design engineer

Company Description AndGate Informatics Pvt. Ltd. is a technology and staffing company founded by industry professionals with extensive experience in semiconductors, IT/software, and recruitment. The organization provides specialized technological solutions and talent services across semiconductor, embedded systems, and software domains. With more than 20 years of collective experience in India and overseas, AndGate operates with a global team supporting clients in India, Malaysia, Singapore, Vietnam, Taiwan, the US, and the UK. Core expertise spans ASIC design and verification, DFT, physical design, analog and mixed-signal engineering, FPGA design, embedded and IoT, database engineering, AI, and machine learning. The company focuses on pairing deep technical knowledge with long-term career opportunities for semiconductor professionals.
Role Description This is a full-time, on-site RTL ASIC Design Engineer role based in Bengaluru. The engineer will be responsible for translating architectural specifications into high-quality RTL, performing RTL coding, and ensuring logic correctness and design robustness. Day-to-day activities include micro-architecture definition, RTL implementation in Verilog/SystemVerilog or VHDL, functional simulation, and close collaboration with verification, DFT, and physical design teams. The role involves debugging design issues across simulation and implementation stages, supporting timing closure, and contributing to design reviews and documentation. The engineer will also work with cross-functional stakeholders to meet power, performance, and area (PPA) targets and to support silicon bring-up as needed.
Qualifications

• Strong RTL Design and RTL Coding skills, including experience with Verilog/SystemVerilog or VHDL for complex digital blocks.
• Solid foundation in Logic Design concepts, including state machines, pipelining, clocking, and low-power digital design techniques.
• Understanding of Physical Design considerations and implementation constraints (timing, area, power) to create physically aware RTL.
• Experience with Formal Verification methods and tools to ensure functional correctness and enable sign-off-quality verification.
• Familiarity with ASIC design flows, simulation tools, synthesis, STA, and linting; exposure to DFT and verification environments is a plus.
• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field (or equivalent practical experience).
• Ability to collaborate in cross-functional teams, communicate technical concepts clearly, and take ownership of assigned design blocks.
• Prior experience in semiconductor product development, from concept to tape-out, and exposure to advanced technology nodes is advantageous.