Physical Design and Implementation Engineer, ASIC

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience in Physical Design.
  
• Experience in high performance synthesis, PnR and sign-off optimizations, sign-off convergence, including Static Timing Analysis (STA), electrical checks and physical verification.
  
• Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Knowledge of Verilog/SystemVerilog.
  
• Understanding of circuit design, device physics and deep submicron technology.
  
• Excellent scripting skills with languages such as Python, Tcl, or Perl.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities:

• Develop high-performance hardware and software to enable Google’s continuous innovations in working with Application Specific Integrated Circuits (ASIC) as a physical design and implementation engineer.
• Collaborate with architects and logic designers to initiate architectural feasibility studies, establish timing, power, and area design objectives, and investigate Register Transfer Language (RTL)/design trade-offs for physical design closure.
  
• Work with verification and software teams to comprehend and execute the design requirements for clocking and power management.
  
• Develop all aspects of ASIC RTL2GDS implementation for high PPA designs.
  
• Manage block and sub-system level physical implementation and QoR (power, timing, area).