Memory Design Engineer

Company Description Vicharak is redefining computing by developing reconfigurable hardware that adapts to software needs in real time, overcoming the limitations of traditional Von Neumann CPU architectures. The company focuses on creating consumer-ready Reconfigurable Computing platforms that deliver higher speed, efficiency, and true parallelism through multiple configurable hardware instances. By rethinking computing architectures, software paradigms, and hardware capabilities from the ground up, Vicharak aims to unlock new levels of performance for everyday applications. Team members have the opportunity to work on foundational technologies that push the boundaries of modern computer architecture and shape the next generation of computing systems.
Role Description As a Memory Design (ASIC) Engineer at Vicharak, you will design, develop, and verify on-chip memory architectures and macros for next-generation reconfigurable computing platforms. This full-time, on-site role is based in Surat and involves close collaboration with architecture, RTL, and physical design teams to translate system requirements into robust, efficient memory subsystems. Your day-to-day work will include specifying memory requirements, modeling and implementing memory blocks, running simulations and verification, and optimizing for performance, area, and power. You will participate in timing closure, sign-off analysis, and silicon debug, ensuring that memory designs integrate seamlessly into complex ASICs. The role also involves contributing to design methodologies, documentation, and continuous improvement of internal flows and tools.
Qualifications

• Strong Circuit Design and device-level understanding for robust, low-power, high-performance memory implementations.
• Solid Logic Design and Computer Architecture skills to define and optimize memory hierarchies, interfaces, and protocols.
• Proficiency in RTL Design (e.g., Verilog/SystemVerilog) for modeling memory controllers and related logic.
• Experience in Physical Design aspects of memory integration, including floorplanning, timing closure, and sign-off.
• Knowledge of ASIC design flows, verification methodologies, and tools (simulation, STA, formal verification).
• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• Ability to work collaboratively in a cross-functional hardware team, with clear, concise communication.
• Experience with memory compilers, SRAM/ROM design, or prior tape-out experience is a strong plus.
• Familiarity with reconfigurable or parallel computing architectures is beneficial.