Lead ASIC RTL Design Engineer

Lead ASIC RTL Design Engineer

Exp-(6–12 Years)

Location: Bengaluru, India

Role Overview

We are looking for a highly skilled Lead ASIC RTL Design Engineer with strong expertise in microarchitecture definition, RTL development, and ASIC implementation. The ideal candidate will have hands-on experience in designing high-performance, power-efficient digital IPs and SoCs, translating architectural specifications into robust RTL implementations.

Key Responsibilities

• Drive microarchitecture development for complex ASIC/SoC blocks, balancing performance, power, area, and scalability requirements.
• Develop high-quality RTL using Verilog/SystemVerilog for complex digital designs.
• Define datapath, control logic, pipeline architecture, clocking strategies, and state machines.
• Collaborate closely with architecture, verification, physical design, DFT, and firmware teams throughout the development cycle.
• Create detailed design specifications, microarchitecture documents, and implementation plans.
• Perform RTL linting, CDC/RDC analysis, low-power checks, and design quality signoff.
• Support synthesis, timing closure, power optimization, and silicon bring-up activities.
• Analyze and resolve functional, timing, and implementation issues across the ASIC development flow.
• Drive design reviews and ensure adherence to coding guidelines and design methodologies.

Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
• 6–12 years of ASIC/SoC RTL Design experience.
• Strong expertise in digital design fundamentals, computer architecture, and microarchitecture development.
• Proficiency in Verilog/SystemVerilog RTL design.
• Experience with pipelined architectures, cache controllers, memory subsystems, interconnects, and high-performance datapaths.
• Strong understanding of ASIC design flow including RTL-to-GDSII.
• Hands-on experience with synthesis, STA concepts, CDC, RDC, lint, and low-power methodologies.
• Familiarity with industry-standard EDA tools from Synopsys, Cadence, or Siemens EDA.
• Experience with scripting using Python, Perl, or Tcl for design automation.
• Strong debugging, problem-solving, and design optimization skills.

Preferred Skills

• Experience in CPU, GPU, AI/ML Accelerator, Networking, Storage, or High-Speed Interface designs.
• Knowledge of AMBA AXI/AHB/APB protocols and on-chip interconnect architectures.
• Exposure to low-power design techniques including UPF/CPF.
• Understanding of DFT, scan insertion, and silicon validation activities.
• Experience working on advanced process nodes (7nm, 5nm, 3nm) is a plus.

What We're Looking For

• Deep microarchitecture ownership mindset.
• Ability to convert architecture specifications into optimized RTL implementations.
• Strong technical leadership and cross-functional collaboration skills.
• Passion for building high-performance silicon products from concept to tape-out.