Junior FPGA Design Engineer

Digantara is a leading Space Surveillance and Intelligence company focused on ensuring orbital safety and sustainability. With expertise in space-based detection, tracking, identification, and monitoring, Digantara provides comprehensive domain awareness across regimes, allowing end users to have actionable intelligence on a single platform. At the core of its infrastructure lies a sophisticated integration of hardware and software capabilities aligned with the key principles of situational awareness: perception (data collection) , comprehension (data processing) , and prediction (analytics) . This holistic approach empowers Digantara to monitor all Resident Space Objects (RSOs) in orbit, fostering comprehensive domain awareness.

Digantara is seeking a passionate Junior FPGA Design Engineer to design and develop RTL modules for the satellite payload . The engineer will be responsible for implementing high-speed data interfaces and robust control interface blocks in the satellite payload's FPGA/SoC.

Why Us?

• Be part of a collaborative and innovative environment where your ideas and skills make a real difference to the entire space realm.
• Push the boundaries with hands-on experience, greater responsibilities, and rapid career advancement.
• Competitive incentives, galvanising workspace, blazing team, frequent outings—pretty much everything that you have heard about a startup.
  
  

Ideal Candidate

• Someone with strong fundamentals in digital logic design and RTL coding experience with AMD-Xilinx/Microchip FPGA/SoC devices
  
  

Responsibilities

• Design high-performance RTL modules for the FPGA/SoC-based payload electronics
• Develop custom IP blocks and test bench modules in VHDL/Verilog
• Collaborate with hardware and software engineers to generate RTL module-level design, verification requirements, and validation plans
• Carry out Synthesis, Place and Route, and static timing analysis (STA) of the FPGA design
• Document the FPGA design, verification, and validation results during the development lifecycle
  
  

Required Qualifications

• B.Tech/B.E in Electronics Engineering or M.Tech/M.E Microelectronics/Embedded systems/VLSI. Final semester undergraduate/graduate students are eligible to apply.
• Up to 1 year of experience in RTL design with working knowledge of FPGA design flow using AMD-Xilinx Vivado/Libero EDA tools.
• Proficiency in VHDL/Verilog-based digital logic implementation.
• Understanding of data communication protocols SPI, I2C, UART, RS422/485, and implementation in FPGA.
• Knowledge of Synthesis and Static Timing Analysis (STA), Place and Route, and FPGA architecture.
• Working knowledge of FPGA/SoC development kits for prototyping and familiarity with electronic test equipment in the lab
  
  

Preferred Skills

• Familiarity with Python or TCL/Perl scripting for automation
• Experience with Questasim or similar tools for functional verification of FPGA design
• Understanding of digital image processing algorithms and implementation on an FPGA
• Knowledge of the latest advancements in FPGA-based digital systems development
  
  

General Requirements

• Ability to work in a mission-focused, operational environment.
• Ability to think critically and make independent decisions.
• Interpersonal skills to enable working in a diverse and dynamic team.
• Maintain a regular and predictable work schedule.
• Writing and delivering technical documents and briefings.
• Verbal and written communications skills as well as organizational skills.
• Travel occasionally as necessary.
  
  

Job Location: Hebbal, Bengaluru

PI270656265