ISP RTL Design Engineer
OMNIVISION ↗
📍 Singapore, Singapore 🇸🇬
full-time
mid-level
Expired
Posted —
This job posting has expired
View All RTL Design Engineer Jobs
Key Skills
VerilogSystemVerilogSystemCRTLC++
Industry
SemiconductorConsumer Electronics
Job Description
Description
Responsibilities
Responsibilities
- Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)
- Verify Logic at ISP level and Digital System level
- Optimize Design for less gate count and low power consumption
-
Drive ISP Design activities in close collaboration with ISP Algorithm Team
- Minimum MSEE, or BSEE, or related/equivalent discipline
- Experience / knowledge in RTL, C/C++ programming and verification
- Strong debugging and problem-solving skills
- Good communication and interpersonal skills
- Result oriented and embrace change behaviours
- C++/SystemC knowledge with High Level Synthesis experience is a plus.
- Experience / knowledge in CMOS Image Sensor is a plus
Featured Opportunities
Similar Jobs
Companies Hiring RTL Design Engineer
Key Skills
VerilogSystemVerilogSystemCRTLC++
Industry
SemiconductorConsumer Electronics
Join the Live Jobs Feed
- Instant Telegram alerts for top jobs
- Organized by specialization and region
- Connect & chat with fellow engineers
Free forever • No spam • Leave anytime