FPGA Verification Engineer

🚀 Hiring: FPGA Verification Engineer | R&D Position | Central Israel

A leading defense company in central Israel is looking for an FPGA Verification Engineer to join a professional development team working on advanced programmable logic (FPGA) solutions for cutting-edge technological projects.

Role Responsibilities:

🔹 Developing and running Random-Based Verification environments

🔹 Developing Verification environments using SystemVerilog UVM methodology – from Test Plan definition, through Random Constraints , to Functional Coverage implementation

🔹 Supporting and enhancing existing Legacy Verification environments using Verilog / VHDL / SystemVerilog

🔹 Writing automation scripts using Python and TCL

🔹 Integrating Verification environments and implementing Functional Coverage

Mandatory Requirements:

✔ B.Sc. in Electrical Engineering / Electronics Engineering

✔ At least 3 years of experience in Verification

✔ Proven experience developing Verification environments based on UVM methodology and Reuse principles

✔ Experience working with UVM Scoreboard and UVM Register Model

✔ Experience with Verification environment integration

Significant Advantages:

⭐ Experience with Assertion-Based Verification (ABV)

⭐ Familiarity with VIPs and their integration into Verification environments

⭐ Experience with communication protocols such as AXI, SPI, I2C, Ethernet, PCIe

⭐ Experience developing with VHDL and Verilog

📩 If you are looking for your next challenge in the FPGA & Verification world, we would love to hear from you. Send your CV or reach out via private message.